Advances in semiconductor device fabrication processes have led to scaling of device dimensions which has resulted in improvements in device performance and cost. For CMOS transistor devices, after significant scaling over the years, due to limitations in gate-oxide thickness and source/drain (S/D) junction depth, it appears that the scaling limit is being approached, where more shrinking will not boost performance because of leakage, power dissipation and tunneling effects. Thus, techniques, other than scaling, are being considered in order to maintain and/or improve device performance for smaller device sizes. Strain engineering is one such technique.
Strain engineering involves straining of the semiconductor crystal to increase the mobility of charge carriers in the channel (electrons in N-channel MOSFET (NMOS) devices and holes in P-channel MOSFET (PMOS) devices). Device performance may be improved with enhanced carrier mobility. Compressive strain is induced in silicon-based PMOS devices, typically using epitaxially grown silicon and germanium SiGe in the source and drain regions of the device. This is known as a source/drain stressor structure. In silicon-based NMOS devices, a tensile strain is used. By adding stress to a channel of a transistor, the carrier mobility in the channel is enhanced which increases the drive current of the transistor but without impacting negatively other device parameters such as off-state leakage.
In a conventional process flow to fabricate a source/drain stressor structure in a transistor device, as shown for example in U.S. Pat. No. 6,861,318, the source/drain recesses are etched in a silicon substrate to the desired depth of the stressor structure and material, typically SiGe, is epitaxially deposited in the etched recesses. The epitaxially deposited material may be doped in-situ (in other words, the strained material includes a dopant in addition to silicon and germanium), while in other cases the deposited SiGe is implanted with dopants which are then activated using a thermal anneal process.
A disadvantage to using the SiGe S/D stressor structure for general purpose or low power applications (for example, in battery operated applications such as mobile devices) is that the SiGe as a material has inherently higher junction leakage than silicon and in many cases defects are formed at the interface between the SiGe and the silicon substrate that also can form leakage paths through the junction. This may result in power being wasted due to junction leakage.
There is therefore a need to provide a semiconductor device which uses strain engineering but which attempts to reduce junction leakage.